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Lab 2 – BCD to 7 Segment Decoder
Description
1. Introduction
A BCD to 7 segment decoder is a combinational logic circuit that accepts a decimal digit in BCD as an input and generates appropriate outputs for the segments to display the input decimal digit. An example of the block diagram of the BCD to 7 segment decoder is shown in the figure below.
Figure 1. Block diagram of a BCD to 7 segment decoder.
2. Description
The purpose of this lab is to design a Binary Coded Decimal (BCD) to 7 segment decoder using Verilog HDL and the FPGA development board of your choice. The inputs of your decoder should be the switches positions corresponding to the binary value of the displayed segment, and the outputs should be the control signals for each of the 7 segments. A block diagram of the FPGA design is shown in Figure 2.
Figure 2. FPGA implementation BCD to 7 segment decoder.
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While the Verilog code for BCD to 7-segment decoder is straightforward, based on the FPGA boards of your choice, the implementation of the switch inputs and the 7-segment display may vary. For the MiniZed board, you will need to use external switches and 7-segment display device along with a breadboard for running your FPGA implementation. If you use a MiniZed board with an external 7-segment display module, resistors (typically from 100? – 1K?) are needed for limiting current flow to protect LEDs in the segments from burning out, as shown in Figure 3. For the Basys 3 board, switches and 7-segment display module are included on the board.
Figure 3. Use of resistors for LED protection in 7-segment display.
You will need to check whether a 7-segment display is Common Anode or Common Cathode before wiring it. An example of 7-segment display checking can be found here:
If you use a MiniZed board, the IOs of the BCD to 7 segment decoder will be provided at the Peripheral module (Pmod) interface or the Arduino-compatible shield interface available on the board. Here we show an example of the Pmod interface. The Pmod interface on the Minized Board include two 12-pin Pmod connectors. The pin assignments of the two Pmod connectors are shown in Figure 4.
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Figure 4. Pin assignment for the two Pmod connectors on the Minized board.
For MiniZed board, in order to associate the Pmod pins to the FPGA implementation (decoder IOs), you will need to add a physical constraint file in the design. An example of adding a physical constraint for pin #1 of the connector Pmod1 for the Verilog signal pmod1_0[0] is shown below:
In this example, we constrained pin #1 of the connector Pmod1 (represented by pinout L15) as 3.3V IO, and associate this pin to the signal pmod1_0[0] in our Verilog code. The correspondence between Zynq bank pinout and Pmod connectors can be found in the MiniZed Board Schematic file available at Avnet website:
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Figure 5. MiniZed Board Schematic showing pin assignment info on the constraint file.
More details on how to add constraint files in the design can be found in the tutorials in “Modules” -> “Tutorials” in Canvas.
3. Deliverables
Write a Verilog description of the BCD to 7 segment decoder. Demonstrate display of different decimal values on the 7 segment decoder for different decoder inputs.