lab1 report

Description

Digital Logic Laboratory

Lab 1 – Introduction of Hardware Description Language (HDL)
1. Introduction
The purpose of this lab is to refresh your memories on HDL design using Verilog and become
familiar with the Xilinx Vivado Design Suite. Tutorials of using the Xilinx Vivado Design Suite
can be found in Canvas. In this lab, you will need to write a Verilog code and the corresponding
test bench to implement and simulate a simple Binary Coded Decimal (BCD) counter.
2. Description
Implement a one-digit BCD counter. It should be a synchronous (4-bit) up/down decade counter
with a 4-bit output Q that works as follows: All state changes occur on the rising edge of the CLK
input, except the asynchronous clear (CLR). When CLR = 0, the counter is reset regardless of the
values of the other inputs. You can select an appropriate number of your period (e.g. 10ns) of the
CLK signal for simulating your design.
Figure 1. BCD counter block diagram.
The expected functional behavior of the BCD counter is described below:
· If the LOAD = ENABLE = 1, the data input D is loaded into the counter.
· If LOAD = 0 and ENABLE = UP = 1, the counter is incremented.
· If LOAD = 0, ENABLE = 1, and UP = 0, the counter is decremented.
· If ENABLE = 1 and UP = 1, the carry output (CO) = 1 when the counter’s value is 9.
· If ENABLE = 1 and UP = 0, the carry output (CO) = 1 when the counter’s value is 0.
3. Deliverables
Write a Verilog description of the counter. You may implement your design in any style you wish.
It will be easier to use a behavioral description which can be either written in the algorithmic way

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(e.g. Count <= Count + 1) or a state machine way (e.g. State <= Next_State). You may also use
dataflow or structural descriptions, although that will be more work. Use the following simulation
for your waveforms:
1. Load the counter with the last digit of your Red ID number.
2. Increment the counter four times.
3. Decrement the counter once.
4. Clear the counter